Due to the ever-increasing demand for portability and high functionality, system integration becomes inevitable to successful product development and marketing leadership.

The objective of this three-hour short course is to study advanced electronic packaging technologies that will enable the industry to achieve the integration goal. Attendees will master the technical concepts of advanced packaging technologies, with emphasis on process, performance advantages, and reliability challenges.

Attendees are expected to have a general knowledge of electronic packaging (e.g., Introduction to Electronic Packaging).

Course Outline:

  1. Introduction: Market need for system integration
  2. The fundamental concepts of System-on-Chip (SOC); Multi-chip Module (MCM); System-in-Package (SiP); System-on-Package (SOP)
  3. Stacked dues, stacked packages (PoP): 1st generation (WB to WB) and 2nd generation (WB to Flip chip)
  4. Fan-out wafer-level packaging (FO-WLP), Fan-Out Panel Level Packaging (FO-PLP), and 3rd generation of PoP
  5. Embedded passive and active
  6. Through-Silicon Via (TSV)
  7. 2.5 D including chiplet and Embedded Multi-die Interconnect Bridge (EMIB); and 3-D integration


Prof. Bongtae Han
301-405-5255 | education@calce.umd.edu | bthan@umd.edu
Bldg. 89, Room 1103
University of Maryland
College Park, MD 20742