Temperature, Humidity Bias

Stress Test Background

Temperature humidity tests are typically used to evaluate reliability of non-hermetic packaged devices in humid environments. With the combination of high temperature and humidity, penetration of moisture through external protective material or along interfaces is accelerated and the ‘moisture resistance’ of the device under test can be evaluated. Some common forms of these tests include the Highly Accelerated temperature and humidity Stress Test (HAST), also known as the Pressure Cooker Test (PCT), which combines pressure with temperature and humidity.

It is also a common practice to combine temperature humidity with voltage bias (THB) for component testing to assess the reliability of a device under humid environment.

THB is also used by the electronics industry as qualification tests to assess the likelihood of Electrochemical-induced failures on printed wiring boards. Simulating a humid, operating environment, the ability of this stress to uncover some common defects in electronic systems is evaluated.

Stress Profile Description

Due to different variations of temperature humidity tests, there is a great variation in stress profiles. Some temperature humidity test parameters described in common standards are included in Table I. Since the effects of the combination of temperature and humidity on board level is being evaluated, a similar stress profile described in JESD 22-A110E is considered. However, the change in stress profile parameters may be needed for a board level application

Parameters Determination

Stress Level- Bias Voltage, Temperature, Humidity

For qualification purposes, the recommended bias voltage ranges from 5V to 50V; temperature ranges from 40°C to 85°C, while humidity ranges from 85% to 93% RH from the different standards listed below. However, the value should be adjusted based on factors such as test purpose, product specifications and knowledge of existing defects.

For design improvement purposes (HALT) in general, stress levels to be high enough to precipitate defects that can cause failures below the desired stress limits or before the desired lifetime.

For screening purposes (HASS, ESS), target stress levels should be set lower to allow for sufficient remaining lifetime of the population with less critical defects remain in the products.

Duration

For qualification purposes, the duration of tests from the standards below range from 72 to 500 hours. However, the value should be adjusted based on factors such as test purpose, product specifications and knowledge of existing defects.

For design improvement purposes (HALT) in general, a longer duration can be appropriate for more defects to be precipitated and corrected for field robustness of the product.

For screening purposes (HASS, ESS), also depend on the stress limits being decided, remaining life of the good population should be taken into account when deciding dwell time.

Standards with Stress Test Description

For qualification purposes

IPC-TM-650 Section 2.6.3.3B (2006): Test Method Manual: Surface Insulation Resistance, Fluxes

IPC-TM-650 Section 2.6.14.1 (2009): Test Method Manual: Electrochemical Migration Resistance Test

GR-78-CORE Section 13.1.5 (1997): General Requirements for the Physical Design and Manufacture of Telecommunications Products and Equipments- Electromigration Resistance Test

J-STD-004B (2008): Requirements for Soldering Fluxes- Surface Insulation Resistance

IEC 61189-5 (2015-2016): Test Methods for Electrical Materials, Printed Boards and other Interconnection Structures and Assemblies- Part5

Potential Defects Precipitated by this Stress

Table I. Example Test Conditions [1]

References

[1] S. Zhan, M. H. Azarian and M. Pecht, "Reliability of Printed Circuit Boards Processed Using No-Clean Flux Technology in Temperature–Humidity–Bias Conditions," IEEE Transactions on Device and Materials Reliability, vol. 8, no. 2, pp. 426-434, June 2008.