Michael Hopkins, Founder/CEO, CurrentRF

Abstract: All digital and DSP based integrated Circuits generate a power line time and frequency domain signature that is the result of the logic function and characteristics of the circuit itself. For CMOS circuits, signature is generated by the overlap current drawn by each logic cell in the design. Given a specific circuit architecture, a specific power line signature is generated. If the logic in the IC is changed, or even if the exact architecture is copied and implemented on a different manufacturing process, the time domain and spectral signatures will change. A simple electrical technique for detection of the above described “counterfit” technology is to simply AC couple the supply line of a given IC on the IC package/evaluation PCB into a spectrum analyzer and record the spectrum over a certain bandwidth. This supply line, AC coupled monitoring avoids the RF losses induced by the Friis equation and antenna effects of the given IC and evaluation PCB, yielding a higher bandwidth and magnitude signal for analysis. Using this simple technique, using a consistent, repeatable stimulus, run a generated evaluation pattern and record the power spectrum of a representative sample of known good parts. Secondly, keeping all dependent variables the same (supply voltage, temperature, etc.), run the same consistent, repeatable stimulus pattern used for the known good sample on the suspect ICs. With the generated known good database, compare the suspect IC generated spectrum against the known good database. If the power line signature significantly changes, a counterfit IC is detected. CurrentRF has used the above testing paradigm on it’s evaluation boards for it’s products. The methodology has yielded the detection of subtle difference in known good ICs and counterfit parts. Differences in performance with respect to temperature and supply voltage deltas have been detected.