Advanced Physical Analysis of Integrated Circuits for Tampering Detection

Dr. Horst Gieser [Fraunhofer EMFT]

Abstract: 

As parts of the IC production, e. g. design, and manufacturing, are distributed worldwide this supply chain is vulnerable to malicious attacks at certain points. Such attacks include unwanted modifications of the design and IC hardware like the insertion of HW trojans as well as the exchange of the IC devices with counterfeits in the final product. Due to such threats occurring more and more in the past methods to check the authenticity of existing semiconductor products for security assurance are highly necessary. In the case of hardware modifications hidden inside the IC across its whole 3D assembly, the ability for full layer-by-layer reverse engineering of integrated circuits is key for their successful detection which finally achieves trust in critical devices from global supply chains. This RE flow includes the analysis and deprocessing of the chip combined with highly precise imaging by means of electron and ion beam chip scanning for final layout extraction and comparison with the original IC design. While the feature sizes of ICs shrink to a few nanometers the thickness of layers is reduced to some ten nanometers. One challenge of tackling physical and technical limits is to achieve homogeneity across several mm chip dimensions as a prerequisite for further full-chip imaging. In our talk, we present today’s methods and preparation results from our CC-EAL6-certified analysis lab for chip technologies down to 7 nm.

Biography: 

Dr. Horst A. Gieser is head of the AT (Analysis and Test) team at the Fraunhofer Institute for Microsystems and Solid State Technologies EMFT. He received his diploma in Electrical Engineering and his Ph.D. from the Technical University in Munich, where he started his first laboratory and research team for analysis and testing in 1989 and transferred it to Fraunhofer in 1994. Starting and growing with electrostatic discharge ESD, he has extended his research and application interest into the field of analysis for trusted electronics, from the nanoscale to the cryo-characterization of quantum devices. He supervises the certified CC-EAL6 lab for the physical analysis of security chips. Since 1992, he has been a member of the standardization of ESD test methods with a focus on discharges in the ps-domain of CDM, and since 2022, he has served as a liaison for the German and Bavarian Trusted Electronics program to the SAE WG19A Counterfeit Detection. He has served at several international conferences in various positions. Mainly in the field of ESD, he has authored and contributed to more than 120 publications, including several invited talks at international conferences in the US, Taiwan, Japan, and Europe. He is the author of book chapters and several publications in peer-reviewed journals. Four of his publications won awards. He is now enjoying very much guiding and assisting a team of enthusiastic young researchers in their mission towards secure and authentic electronics.