Abstract: 

As parts of the IC production, e. g. design, and manufacturing, are distributed worldwide this supply chain is vulnerable to malicious attacks at certain points. Such attacks include unwanted modifications of the design and IC hardware like the insertion of HW trojans as well as the exchange of the IC devices with counterfeits in the final product. Due to such threats occurring more and more in the past methods to check the authenticity of existing semiconductor products for security assurance are highly necessary. In the case of hardware modifications hidden inside the IC across its whole 3D assembly, the ability for full layer-by-layer reverse engineering of integrated circuits is key for their successful detection which finally achieves trust in critical devices from global supply chains. This RE flow includes the analysis and deprocessing of the chip combined with highly precise imaging by means of electron and ion beam chip scanning for final layout extraction and comparison with the original IC design. While the feature sizes of ICs shrink to a few nanometers the thickness of layers is reduced to some ten nanometers. One challenge of tackling physical and technical limits is to achieve homogeneity across several mm chip dimensions as a prerequisite for further full-chip imaging. In our talk, we present today’s methods and preparation results from our CC-EAL6-certified analysis lab for chip technologies down to 7 nm.

Biography:

Nicola Kovac [Fraunhofer EMFT]

Nicola Kovac received his Master's degree in Micro- and Nanotechnology from the Munich University of Applied Sciences. Since 2018, he is part of the team ‘Analysis & Test’ at the Fraunhofer Research Institute for Microsystems and Solid State Technologies EMFT in Munich (Germany). There, he works as a scientist and process engineer in the field of physical analysis for authenticity assurance and security of integrated circuits. Pursuing a PhD-degree, he develops and applies the most advanced methods and processes for homogeneous large-area delayering and precise characterization to devices from the latest technology nodes.

Dr. Horst Gieser [Fraunhofer EMFT]

Dr. Horst A. Gieser is head of the AT (Analysis and Test) team at the Fraunhofer Institute for Microsystems and Solid State Technologies EMFT. He received his diploma in Electrical Engineering and his Ph.D. from the Technical University in Munich where he started his first laboratory and research team for analysis and testing in 1989 and transferred it to Fraunhofer in 1994. Starting and growing with Electrostatic Discharge ESD, he has extended his research and application interest into the field of the analysis for Trusted Electronics down to the nanoscale and most recently the cryo-characterization of quantum devices. He supervises the certified CC-EAL6 lab for the physical analysis of security chips. Since 1992 he has been a member of the standardization of ESD test methods with a focus on discharges in the ps-domain of CDM and since 2022 he serves as a liaison for the German and Bavarian Trusted Electronics program to the SAE WG19A Counterfeit Detection. He has served at several international conferences in various positions. Mainly in the field of ESD he has authored and contributed to more than 120 publications including several invited talks at international conferences in the US, Taiwan, Japan and Europe. He is the author of book chapters and several publications in peer-reviewed journals. Four of his publications won awards. He is now enjoying very much guiding and assisting a team of enthusiastic young researchers in their mission towards secure and authentic electronics.

Dr. Tobias Zweifel [Fraunhofer EMFT]

Tobias Zweifel graduated in Experimental Physics at the University of Regensburg, specializing in the field of single electron transistor development. Afterward, he joined the Technical University of Munich where he received his Ph.D. in the field of Material Science. Subsequently, he joined RoodMicrotec’s failure analysis team for several years before joining the Analysis & Test team of Fraunhofer-Institute for Microsystems and Solid State Technologies EMFT in 2019. Since then he has been working in the field of IC failure analysis and reverse engineering, specializing in large-scale chip scanning, image processing, and IC layout extraction for modern technologies with feature sizes down to a few nanometers.

Dominik Muß [Fraunhofer EMFT]

Dominik Muß has successfully completed his Master of Science in Physics at Leopold-Franzens-University in Innsbruck. He completed his undergraduate studies in applied physics at the university of applied science in Munich. Since 2021, he has headed the group for failure and reliability analysis at the Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT. One of the main areas of work is the characterization of assemblies and complex electronic systems using advanced measurement and analysis techniques as well as robustness evaluations based on environmental simulations. Furthermore, existing methods such as high-resolution X-ray technology are continuously optimized for use in microelectronics.