CALCE Webinar - Investigation of Copper RDL Early Fatigue Failure in WLCSP Under Thermal Cycling

Tuesday, December 10, 2019
11:00 a.m.-12:00 p.m.

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Abstract

Redistribution layer (RDL) architectures, used in wafer-level chip scale packages (WLCSP) and in interposers for heterogeneous integration, present the possibility of multiple degradation modes under thermal cycling and power cycling:

  1. fatigue cracks in the copper redistribution layer;
  2. fatigue cracks in PBO dielectric layer;
  3. failure at various interfaces between the PBO and copper layers; and
  4. cracks in the die active and passivation layers.

Several materials are involved in these failure modes: (i) seed layers and copper used in the UBM and RDL layers/features; (ii) PBO layers used as a dielectric; (iii) Oxide passivation layer; and (iv) Silicon semiconductor. The cracks usually propagate though one or more of these materials and/or along the interfaces separating them. The motivation for this project is to lower the risk of RDL failures, by assessing and diagnosing the root cause(s) of the fatigue cracks discussed above.

Cyclic fatigue test coupons, consisting of representative copper traces on silicon wafers, were specially designed and fabricated in this study for investigation of the cyclic fatigue durability of RDL copper. The characteristic dimensions of the copper traces were selected to be comparable to those in WLCSP RDLs. However, there are several significant differences between the Cu-on-Si test coupons and the WLCSP specimens. First, the copper trace fabrication methods are significantly different, and second, the Cu-on-Si specimens do not contain the PBO dielectric layers that are extensively used in the WLCSP RDL architecture. The Cu-on-Si specimens were first subjected to mechanical cycling, using cyclic bend testing and vibration testing, at strain levels similar to those estimated with finite element analysis (FEA) for thermal cycling of WLCSP RDL structures. Subsequently, thermal cycling tests were also conducted on the Cu-on-Si test coupons. These accelerated tests reveal that the copper traces in these Cu-on-Si test coupons are significantly more fatigue resistant under mechanical and thermal cycling, than RDL traces in WLCSP.

Three possible reasons are postulated for this apparent difference in fatigue durability:

  1. the copper microstructure in Cu-on-Si test coupon is significantly different from the copper microstructure in WLCSP specimens due to differences in the fabrication methods;
  2. Mechanical cycling is not as same as thermal cycling (potentially due to cyclic thermal aging of the copper microstructure);
  3. Effect of thermal cycling is not the same in the Cu-on-Si test coupons and in the WLCSP specimens, because of: (a) cyclic thermal aging and damage in the PBO dielectric PBO-Copper interfaces in the RDL architecture; and (b) difference in thermal aging of the copper conductors
  4. Prior FEA of thermal cycling of WLCSP had underestimated the true strain level in RDL traces because the effect of PBO damage was not considered.

Based on accelerated stress testing and new error-seeded finite element modeling, all the factors listed above have been examined in this study and are found to have the potential for influencing RDL copper fatigue vulnerability in WLCSP specimens under thermal cycling. In particular, new detailed error-seeded FEA revealed that the thermo-mechanical fracture and delamination damage observed in the PBO dielectric has a significantly deleterious effect on the stress levels in the copper traces. Future work should focus on quantifying these risks and also on managing the risks by ruggedizing the PBO-Cu architecture.

About the Presenter: Qian Jiang is a Ph.D. candidate in Mechanical Engineering and a graduate research assistant at CALCE. Her dissertation research is in the field of anisotropic creep and elastic behavior of SnAgCu solder alloy, based on the microstructure and mechanistic modeling approaches. She has worked on several other CALCE research projects, notably the characterization on properties and durability of solder materials under various temperature/loading conditions, and fatigue failure in Cu redistributions layers on wafer level chip scale package. Ms. Jiang is being advised by Professor Abhijit Dasgupta.

 

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